Problem Statement - Some improvements should be done in order to increase the speed of JTAG protocol specially in architecture of protocol.
Challenge description with context - JTAG implements standards for on-chip instrumentation in electronic design automation (EDA) as a complementary tool to digital simulation. It specifies the use of a dedicated debug port implementing a serial communications interface for low-overhead access without requiring direct external access to the system address and data buses. If any modification is to be done which can increase the standard speed.
Problem – Speed improvement of existing architecture of JTAG protocol which tends to have faster operational and functionality speed and better results.
Users – Industrial experts in chip designing
Expected Outcomes - Doubles the speed. More convenient protocol design is possible.